1. Field of the Invention
The present invention relates to a computer system having hierarchical storage, more particularly, to a system for controlling access to a channel buffer in the computer system.
2. Description of the Prior Art
In general, a computer system comprises a main storage unit (MSU) for storing data and instructions, a central processing unit (CPU) for performing those instructions, a channel processor (CHP) including a plurality of channels, and a memory control unit (MCU) for controlling data transmission therebetween. In this computer system, in order to increase the throughput of access of the channels to the MSU and, in addition, in order to interrupt the access of the CPU to the MSU, a channel buffer (CHB) is provided in the MCU. The CHB is used for controlling data transmission between the CHP (or the channels) and the MSU. That is, when one of the channels requests a fetch, a predetermined amount of data including the fetch-requested data is transmitted from the MSU to the CHB, then the fetch-requested data is transmitted from the CHB to the channel. In this case, if the above-mentioned amount of data is already loaded in the CHB, the fetch-requested data therefrom is at once transmitted to the channel. On the other hand, if one of the channels requests a store access to the MSU, the data to be stored is temporarily stored in the CHB. After a predetermined amount of data is stored in the CHB, the predetermined amount of data is transmitted from the CHB to the MSU. As a result, the presence of the CHB reduces the probability of a main storage access being concurrently requested by the CPU and the CHP, thereby improving the throughput of the channels.
The CHP (channels) usually accesses continuous memory areas of the MSU, however, if a set associative system which is generally used for cache memories is adopted, the following problems occur:
(a) Since it is difficult to synchronize the access operation of the CHP as compared with the access operation of the CPU, access control becomes complex and, in addition, testing and troubleshooting are difficult.
(b) When the CHB is full of data, it is necessary to perform a "MOVE-OUT" operation prior to the actual access operation, which may invite channel overruns (command/data).
(c) A "RELEASE" operation is necessary. Note that a "RELEASE" operation is carried out to bring all of the contents of the CHB to the MSU when an input/output instruction is initiated and when an interruption is generated at the end of data transmission.
(d) When the CPU requests a store access to the MSU, it is necessary to search whether or not the block requested by the CPU is also present in the CHB. If the block is also present in the CHB, it is necessary to invalidate that block.
(e) The store sequence from the CHP to the MSU is not clear to the CPU. Therefore, if the CPU desires a correct store sequence, it is necessary to carry out additional input/output instructions without data transmission.